Updating Components when Different Number of Gates ?
Posted by restalp at
Good Evening,
I'm currently messing around with a design that includes an FPGA. To make my life easier and my schematics tidier, I've got a project-specific component for the FPGA that is comprised of multiple gates. Each gate covers a specific subset of functionality pertinent to the current schematic (ie. SPI PROM interface), or perhaps just one or two pins for flags.
My problem comes when I shift the gates around a little in the component - maybe add a new gate because there's a slight design change, or add a pin to another gate to consolidate things or make them more legible. If I do this then I get the following error when trying to update the schematics:
Errors accessing items in the library:
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Components:
Cannot update component MSF-NTP-FPGA-SPARTAN6 because there are a different number of gates between the old and new versions.
Now, I also cannot add a new instance of the component and just rewire all the gates up one at a time while removing the old ones, since DesignSpark complains that there is already a 'local copy' in the schematic. This means I need to remove the existing gates from the schematics first !
I got bitten by this earlier in the design and it was a chew-on to revert the gates in the component, then remove the gates from the schematics, re-amend the component and then wire it into the schematics again. I decided to add all the gates I knew about at that point in time, but unfortunately I didn't have as much foresight as required at that point, and I now need to do a further amendment to the FPGA component !
How can I get the FPGA component updated in my schematic without enduring the complete ball-ache of removing all my gates from the schematics (and probably losing a few nets in the process), amending the gates and then re-adding / re-wiring them to the relevant bits in the schematics ?
Please tell me there's a simpler way...!
Also, I should probably just add that so far I'm finding DeisgnSpark to be pretty good, so thanks for releasing this; I hope you put continued effort into further development (forget the eye candy 3D stuff - concentrate on making the schematic capture more slick to save users hours of grief on daft issues like this). Sure, it's got some quirks and bugs, but by and large I like it and plan to use it more. This is my first design with the tool, so I've not tried the PCB layout just yet though !
Help would be very much appreciated with this problem.
Regards,
Pete Restall
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EDIT: Since it's been a few days and no reply I thought I'd bite the bullet and just delete the component from the schematics / re-add it. Unfortunately I get 'an unrecoverable error has occurred' when hitting Delete on one of (any of) the gates. After that, my schematic file is completely goosed (see screenshot - that would usually be a white background with a grid and components on it). Good job I made a backup. Is there a log file somewhere that could tell me what's wrong...? Anybody else got anything similar...?!? This issue is burning time and beginning to frustrate me with what is otherwise a good tool.
Thanks.
Replies
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Peter,
Your problem is that you for some reason think that you can 'program/implement' an FPGA in Desing Spark, and sad to say, you can't! Design Spark is just a PCB tool nothing more, so treath the FPGA as a 'black box' in Design Spark, and implement it with the propper tools. (Xilinx ISE Design Suite)
Also, you are talking about 'gates' and 'nets' ... are you realy sure you need an FPGA for what you are doing? It sound to me that a CPLD, GAL or something in that neighborhood will do what you want to do ... (not to mention that it will be much simpler than an FPGA)
Yours,
Tom
PS : Welcome to the "unrecoverable error club" :-D
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Thanks for the reply Tom, although you've made a few assumptions there that are incorrect.
I have, and am using, ISE to implement the FPGA design - I am using DesignSpark purely for the hardware design (as you point out, I'd have a hard time doing anything else, since it's not in any way, shape or form designed for that). The gates and nets I talk about are DesignSpark's component gates, and DesignSpark's drawing nets.
To make the schematics simpler and more cohesive, I wish to split my FPGA component into separate gates - ie. I have a gate that contains the pins for the SPI flash, which resides on a schematic along with that flash and other related hardware. Think along the lines of the 74* series parts that are already in the component library. What I am trying to avoid is a box in a schematic with a few hundred pins, wired to a few hundred nets - that would not make for a clear diagram, would make errors very difficult to spot and would be very difficult to maintain.
A CPLD or a GAL would not be sufficient for my needs. A DSP-capable MCU, however, would be - but this is an educational project to get me up to speed with the Spartan 6 before I use that part in a more complex design.
Being a member of the 'unrecoverable error' club isn't seeming like much consolation at this point, either :( I think I'll have to find some way of removing the part from my schematics without crashing the program and then re-add it; it doesn't look like DesignSpark will let me manipulate gates in the ways I'm trying to.
Regards,
Pete Restall
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Peter,
Ok, now I get a better idea of your problem :-)
Modern FPGA's are indeed big, but in my experience it doesn't make much senes to re-shape the schematic symbol for the FPGA in a 'readable' form (it takes too much time, and headakes I prefere to spend on the acctual design itself) by the way, you will run into the same kind of problems using other PCB tools like Orcad, Altium and the like ...
Myself, I always model the XC as one big square, this one goes on one sheet together with the flash, reset button ... Then I just name the nets using the ('TO' and 'FROM' off-page symbols).
The only tip I can give you is NOT to try to enforce your pin-names on the Xilinx, keep the original naming convention alive, and instead name the nets leading up to the FPGA to your convenience. The reason for this is that in a later stage (PCB Layout) you will often feel the need to 're-arrange' the position of the nets to accomodate for better routing. In that case it is just a matter of re-naming nets in the schematic, followed by a 'forward design changes'. If however you do enforce your naming, then I found that I made mistakes as one loses the feeling what are the pin's capabilities. (For some reason I almost always end up using multiple IO standards in my designs)
If you still want to split up the FPGA, maybe you can indeed split off the SPI part, the power & ground part and divide the rest of the Xilinx into its banks ...
Ciao,
Tom
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Thanks Tom.
Yes, I was wondering if I should just stick the FPGA on one schematic and air-wire it into the rest of the design. I'd have preferred not to, though.
Unfortunately, it looks like DesignSpark is not very good at sharing gates across schematics. Even the simple parts like the 74HC00 have issues when sharing across more than two sheets - two sheets seems to work alright in the main, but sometimes I find that I still lose components. Very flaky indeed, especially since these errors can cause you to lose work.
Perhaps the best advice until they bottom out these issues is, as you say, keep all gates of one component on a single sheet.
Regards,
Pete Restall