LatticeECP2/M and LatticeECP3 Dual Boot Feature

One of the biggest risks in field upgrade applications is disruption during the field upgrade process. Disruption can
occur as:
• Power disruption
• Communications disruption
• Data file corruption
To eliminate the risk completely, the device will switch to load from the second known good (Golden) pattern when
the first pattern is corrupted. This is the Dual Boot feature, which enhances the reliability of a field upgradeable system.
Even if the system does not require a field upgrade, the pattern corruption can still occur due to the following problems
caused by the SPI Flash devices:
• Read fatigue
• Charge loss
The Golden pattern is less affected by these problems since it is mostly left in a dormant state.
The LatticeECP™ and LatticeSC™ families were the industry’s first FPGA devices to support industry standard
SPI Flash devices as the single image boot PROM. The LatticeECP2/M is the first FPGA family to support the Dual
Boot feature using only one industry standard SPI Flash device. This approach has many advantages:
• Lower cost
– One-chip solution
– Industry standard SPI Flash devices
– Density can be as high as 128 Mbit
• Much smaller board space
– 8-pin SOIC packages for 16 Mbit or less
– 16-pin SOIC packages for 32 Mbit or larger
• Simple field upgrade
– Uses industry standard SPI interface
– Uses JTAG port
• Reliable field upgrade
– Uses the SPI Flash device’s Sector Lock feature to protect the Golden pattern
– Locates the Golden pattern strategically into the locked sectors
The abundant supply of SPI Flash devices offers system designers many low cost system solutions. For example:
• Density ranges from 1 Mbit to 128 Mbit
– One SPI Flash device can store up to two bitstreams with 64-Mbit bits each
• Attractive features that are applicable to the Dual Boot feature:
– Soft Flash Lock by sectors protecting the patterns from erroneous re-programming
– High-speed read at >50 MHz for fast boot-up time
– Power-down option to minimize power consumption